In an integrated circuit using CMOS transistors, characteristics fluctuation exists due to variations in transistor dimension caused by a fabrication process and a change in the environment, such as temperature or supply voltage, during operation.
As described in “1994 symposium on VLSI technology digest of technical papers” (June, 1994), pp. 13 to 14, as an MOS transistor becomes finer, fluctuation in basic parameters, such as a threshold value due to the characteristics fluctuation caused by a fabrication process, becomes larger.
FIG. 12 schematically shows delay of a CMOS circuit with respect to the device feature size of a MOS transistor and the range of variation. In designing a CMOS integrated circuit, the worst delay in FIG. 12 has to be considered. By an increase in the range of variation, even if the device becomes finer, high-speed operation is limited by the worst delay. If the delay of the CMOS circuit can be made “typical” or “best” by suppressing the characteristics fluctuation, the high processing speed of the circuit can be promoted.
As a method of suppressing the characteristics fluctuation by improving the circuit, in Nikkei Electronics 7–28 (1997), pp. 113 to 126, a technique is described as follows: A leakage current of a monitor is measured and a substrate bias is changed so that the current becomes a constant value. Delay of a replica is also measured. A change in delay is detected, and the supply voltage is changed, thereby suppressing the characteristics fluctuation.
According to the technique described in Nikkei Electronics 7–28 (1997), pp. 113 to 126, the substrate bias is controlled so that the leakage current of the MOS transistor when the gate voltage is 0V becomes a constant value. Since the leakage current of the MOS transistor increases as the temperature rises, the threshold has to be increased by applying the substrate bias. In this case, there is a drawback such that the ON current of the MOS transistor conspicuously decreases by deterioration in mobility and increase in the threshold due to the temperature rise, and as a result, the processing speed of the circuit decreases. A filter having an inductance and a capacitance is formed outside of the chip and used to generate a supply voltage for delay control. Since it takes a few μ seconds until an output voltage of the filter is stabilized, stabilization time of a control signal is long, and the signal tends to be unstable. Consequently, control accuracy cannot be raised. When the capacitance and the inductance used for the filter are formed on the same chip on which a circuit to be controlled is also mounted, the fact that they occupy a large area becomes a problem.
Japanese Unexamined Patent Application No. 4-247653 discloses a concept such that a delay detector is provided to suppress delay variations of a gate circuit and the substrate bias of the gate circuit is controlled on the basis of the detection result.
Japanese Unexamined Patent Application No. 5-152935 also discloses a concept such that the substrate bias is controlled by using a capacitive filter and a charge pump to suppress device variations, thereby improving the yield.
Further, Japanese Unexamined Patent Application No. 8-274620 discloses a concept such that the delay amount of a circuit is detected by using a reference clock signal and the substrate bias of the circuit is controlled on the basis of the detection result.